3.2 Simulation Concept

The simulation is performed by discrete time steps. The wiring developer has to consider implications like aliasing effect. At each simulation step each wire has a signal value (may be analog or digital). Systems may have internal states, like the memory of a filter. At the beginning all signal and state values are zero. The transition from step $i$ to $i+1$ is performed by:

• Sources receive a call to calculate their output signal and pass it on to the output wire.
• Wires receiving a signal, pass it on to the connected system.
• `Regular systems' receiving a signal, calculate their output signal(s) and pass them on to the output wire(s).

This simple `straight forward' simulation concept works as far as there are no `irregular systems' with several inputs (like an adder) or a change in sampling rate (like a downsampler) which require a synchronization of different signal paths. The example of figure 1 consists of only one straight forward `simulation chain'. The sink is a special case of a system: it has no outputs and the simulation chain ends.

To overcome the synchronization issues when several signal paths are to be coordinated, the wiring has to be divided into several simulation chains. This is performed in the wiring initialisation procedure by an instance of the object termed WiringAdministator. Each simulation chain can be simulated straight forward. Objects termed SystemContainer represent these chains and they all together manage the constraints of synchronization:

• All SystemContainer try periodically to perform a simulation step.
• Only if all required input signals of a SystemContainer are available and all output signals are handed over, a simulation step can be performed.
• Some SystemContainers may be blocked due to synchronization constraints, but at least one is ready to carry on.

Taken in the lump,

• all conceivable wiring topologies and also different sampling rates of SystemContainers (linked by up- or downsamplers) can be managed (see [Mat97]) and
• developers using labAlive need not to care about the simulation details. Creating an instance of WiringAdministator supplied with all generators (systems without inputs) is all they have to do.